Moore's Law to run out of steam by 2021

Practical limits of Moore's Law to be reached in five years time, claims Semiconductor Industry Association

The practical limits of Moore's Law will be reached as early as 2021, according to the Semiconductor Industry Association (SIA) in its latest International Technology Roadmap.

Moore's Law is the observation that the number of transistors on an integrated circuit doubled around every two years. Coined by Fairchild Semiconductor and Intel co-founder Gordon Moore in a 1965 research paper, Moore's Law has been pretty accurate ever since, confounding sceptics who expected progress to slow as integrated circuits shrank with each successive generation.

But according to the Semiconductor Industry Association's latest roadmap it's going to be all-change as early as 2021. The SIA suggests that even if it is physically possible for chip makers to cram a few more transistors in, it probably wouldn't be financially practical because of the colossal costs of manufacturing them.

And the organisation's latest roadmap through to 2030 is described by president and CEO John Neuffer as the "final instalment".

"Each new technology generation produces faster transistors that can switch faster than those produced with the previous technology generation. In the past, this electrical feature of transistors enabled microprocessors to operate at higher frequencies and, therefore, computer performance as measured by industry benchmarks," suggested the association's report.

But, it continued, computers' fundamental underlying architecture hasn't changed since Hungarian-American mathematician and computer scientist John von Neumann introduced the various core concepts back in 1945.

Until around 2000, each proceeding generation of microprocessors increased in terms of both performance and power consumption until fundamental thermal limits were reached. That is to say, heat generation became an increasing problem.

"Even though the transistor count has kept on increasing... at Moore's Law pace and transistors are able to operate with each new technology generation at higher frequencies than before, it has become practically impossible to keep on conjunctly increasing both of these factors due to physical limitations on power dissipation.

"One of the two features (either number of transistors or frequency) had to level off in order to make the integrated circuits capable to operate under practical thermal conditions. Frequency was selected as the sacrificial victim and it has stalled in the few gigahertz since the middle of the previous decade," continues the report.

As a result, too, the computer industry "has been compelled to develop such methods as complex software algorithms and clever instruction management to improve performance to partially compensate".

At the same time, points out the SIA, the rise of mobile has placed the emphasis squarely on reducing power consumption. And, moreover, chip makers have increasingly struggled to shrink their integrated circuits - from 28nm, to 14nm and, soon, to 10nm. The practical limit in terms of integrated circuits will be reached at around 6nm, if that is financially practical to achieve.

"Geometrical scaling characterised the 1970s, 1980s and 1990s. This was the first generation of transistor scaling. Major material and structural limitations were identified in the mid-90s and the research community initiated the foundation of a new scaling approach that was heralded by the International Technology Roadmap for Semiconductors in 1998. This was named Equivalent Scaling.

"Strained silicon, high-k/Metal gate, FinFET and the use of other semiconductor material (for example, germanium) represent the main features of this scaling approach. As features approach the 10nm range and below it becomes clear that the semiconductor industry is running out of horizontal space."

The SIA anticipates memory, and flash memory in particular, to lead the way for microprocessor technology, with chip makers increasingly resorting to such techniques as 3D packaging and 3D chips, which stacks silicon layer-upon-layer.