PCI Expresss 7.0 could quadruple bandwidth and speed

The final standard could be four times faster than today's PCIe 5.0 spec, but we won't see products till 2026 at the earliest.

The Peripheral Component Interconnect Special Interest Group (PCI-SIG) has unveiled the proposed specification for PCI Express (PCIe) 7.0, promising to offer up to 512 GB/s of throughput: four times faster than the current PCI Express 5.0 rates (128GB/s).

The group announced the new spec at the PCI-SIG Developers Conference 2022, held this week at the Santa Clara Convention Center in California.

The final PCIe 7.0 specifications are anticipated to be published in 2025, while the first PCIe 7.0 devices should be available on the market by 2026/27, if history is any indication.

PCIe technology, which has been around since 2003, is a ubiquitous I/O standard that has almost completely taken over the discrete GPU and SSD market due to its dependability and effectiveness. The technology is scalable for a wide range of products.

The PCI-SIG is in charge of defining PCIe standards, and its primary goal is to double PCIe bandwidth every three years.

The group claims that PCIe 7.0 will double the bandwidth of PCI Express 6.0, from 64 gigatransfers per second (GT/s) (256GB/s speed) to 128 GT/s (512GB/s) over a bi-directional x16 interface - and quadruple PCIe 5.0's rate of 32 GT/s (128 GB/s).

However, this does not take into account the encoding overhead or the impact of header efficiency, both of which affect the total usable bandwidth.

PCIe 7.0 will use PAM4 (Pulse Amplitude Modulation with 4 levels) signalling, which debuted with PCIe version 6.0.

The channel parameters and reach, increased power efficiency, and reduced latency will all be priorities for the future generation. It will also be backwards-compatible with earlier versions of the technology.

The PCIe 7.0 standard is intended to serve data-intensive markets like hyperscale data centres, high-performance computing (HPC) and military/aerospace, as well as new applications like 800G ethernet, cloud, quantum computing and AI/ML.

Al Yanes, president and chairperson of the PCI-SIG, said, "As PCIe technology continues to evolve to meet the high bandwidth demands, our workgroups' focus will be on channel parameters and reach and improving power efficiency."

PCIe 5.0 was first unveiled in 2017, although it is just now beginning to get widespread attention after the first products released late last year.

PCIe 5.0 is included in some of Intel's Alder Lake CPUs, and it is anticipated that the Sapphire Rapids versions of Intel's Xeon server chips will have it before the end of the year.

Epyc server chips from AMD still only support PCIe 4.0, and are not expected to have PCIe 5.0 until versions based on the next-generation Zen 4 cores are released.

Meanwhile, the first devices compliant with the PCIe 6.0 requirements are not expected to hit the markets until next year.