Atom-thin processors fabricated using novel thermal scanning probe lithography

clock • 2 min read

New technique offers several advantages over today's electron beam lithography method

An international team of researchers has devised a novel thermal lithography technique to fabricate atom-thin processors on two-dimensional (2D) semiconductors, such as molybdenum disulphide (MoS2).

The team, which was led by Elisa Riedo, Professor of Chemical and Biomolecular Engineering at New York University (NYU) Tandon School of Engineering, also claims that the new technique provides better results than standard methods for fabricating of metal electrodes on materials like MoS2.

A nanochip is an integrated circuit so small in physical terms that it can only be measured precisely in the nanometre scale. That compares to computers in the earliest years of computing that required rooms or even buildings just to assemble and to operate. 

Each component of the chip has to be created in the atomic scale, meaning each atom of the substrate has to be manipulated to create the tiny components of the nanochip

In the past six decades, scientists have tried to reduce the size of computers and electronic components and have also found success in creating small-sized electronic components that not only work more efficiently but also consume lesser amount of power.

Although researchers have been able to create chip components in the nanometre scale, they are still far from fabricating a complete chip at this scale. For this to happen, each component of the chip has to be created in the atomic scale, meaning each atom of the substrate has to be manipulated to create the tiny components of the nanochip.

The new fabrication method, devised by Riedo's team is called thermal scanning probe lithography (t-SPL) and involves heating a probe above 100 degrees Celsius.

Researchers say t-SPL technique offers several advantages over today's electron beam lithography (EBL) method. The t-SPL method immensely improves the quality of the 2D transistors by offsetting the Schottky barrier, which impedes the flow of electrons at the intersection of 2D substrate and the metal.

With this technique, chip designers can image the 2D semiconductor and pattern the electrodes at desired spots - a facility not available with EBL method.

Another advantage of t-SPL method is its lower operational costs and less power demands. The t-SPL operates in ambient conditions, so it doesn't require high-energy electrons or an ultra-high vacuum to operate.

This new technique can also be scaled up easily using parallel thermal probes to mass produce nanochips.

Riedo hopes their new t-SPL method will help advance chip designing in future by taking chip production out of scarce, expensive rooms into individual laboratories. Further advancement in the technology could help invent t-SPL tools with sub-10 nanometre resolution that will run on standard 120-volt power in ambient conditions.

The findings of the study are published in journal Nature Electronics.

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