HP uses nano technology to shrink chips

Could herald less power-hungry chips, according to computer giant

HP has detailed research that could lead to an eight-fold increase in transistor density in a particular type of chip. The move could enable more complex chips that use less energy for a given computation, according to HP.

The chips involved are field programmable gate arrays (FPGAs), a type of programmable chip used in digital equipment such as network switches. Researchers at HP Laboratories said transistors in future FPGAs could be packed closer together by using nanoscale switching devices to interconnect the logic blocks.

While the research was conducted using modelling and simulation techniques, HP said it is working to produce silicon prototypes using the approach before the end of 2007. Production chips using a 45nm fabrication technology and 15nm wide crossbar wires could be viable by 2010.

“The expense of fabricating chips is increasing dramatically with increasing manufacturing tolerances. We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices,” said Greg Snider, senior architect for Quantum Science Research at HP Labs.