BACKBONE - Intel should watch its back

Intel is having to face up to the stark reality that it is not goingK7 and Compaq's Alpha in the battle for server processors. to have the future of the x86 instruction set to itself. The amount of money it is spending on marketing serves as an indicator of the pressure it is coming under from the likes of Cyrix and AMD. Others, such as IDT, Rise and Transmeta - the company that employs Linus Torvalds - are waiting in the wings.

But in the server space for x86-compatible chips, Intel has up to now remained nearly untouchable. That is starting to change. Compaq is pushing its Alpha processor, which, while not an x86 processor, has the raw performance to run x86 code in emulated form and still compete with native x86 high-end processors.

Later this summer, AMD will unveil its first high-performance server chip to really compete with Intel - the K7. The new, eagerly awaited chip is expected to be a solid performer when it comes to server applications.

In February, AMD was awarded a patent for a circuit that can convert Cisc instructions into Risc code in high-performance processors. This technology will be integrated into the K7 core and is expected to give it a considerable performance boost over its predecessor, the K6-III.

The K7 will also support AMD's 3DNow instructions, which is AMD's competitor to Intel's Streaming SIMD extensions. While these instructions will speed up I/O performance, they are not going to affect the integer performance of the chip. Integer performance is important on server chips as most server apps are integer-intensive.

The real winner for AMD is the speed of the front-side bus on the motherboard for the K7. This will use technology licensed from Digital's Alpha and run at 200MHz - significantly faster than the 133MHz bus due soon from Intel. The chips will come with a Level 2 cache of up to 8MB, which can be achieved using cheap SDRAM.

Despite all this buzz surrounding the K7, Intel's main competitor to its forthcoming IA-64 Merced is the Alpha processor. Alpha is popular as a platform for NT, and with its falling prices, it could become even more of a favourite.

Alpha uses its F32 emulator to run x86 code, as the chip is based on Risc technology rather than the Cisc that is used by Intel. The latest processor in the Alpha family is the catchily named 21264, which was introduced at 575MHz, but is expected to rise to speeds in the 1GHz range.

Compaq unleashes Alpha

Late this year, Compaq will release the 21364 Alpha, which takes the 274 core and integrates an on-die 1.5MB, Level 2 cache with a 128KB Level 1 cache, Direct RDRAM memory controller and a network interface card.

The chip will also be able to access up to 4TB of memory.

While Intel has yet to officially release details of its Merced chip (see box), it does look like its going to have its work cut out to enter the market with not just impressive performance, but also an impressive and realistic price point.

INTEL'S DESIGNS ON MERCED: LEAKED INFORMATION IS REVEALING

Leaked information on Intel's plans for the future of its IA-32 and IA-64 technologies has revealed mechanical details of how its Merced processor will be implemented, writes Mike Magee.

Merced is still on target for release in the middle half of 2000 using 0.18-micron process technology. McKinley will be released in 2001, while Madison, an IA-64 performance part, and Deerfield, an IA/64 price/performance part, follow soon after, using a 0.13-micron process.

Foster's new IA-32 architecture will provide large on-chip Level 1 and Level 2 cache, and give a bus bandwidth of 3.2Gbps, with Level 1 cache performing at 32Gbps and Level 2 cache at 8Gbps.

Intel claims Merced will have 20 times the performance of the Pentium Pro and three times the performance of Tanner on 3D graphics.

Merced will manage memory latency with a three-level cache hierarchy.

That design will include separate instructions and data L0 caches and a larger unified Level 1 cache on the die; the Level 2, which is off the die, will provide large overall capacity.

Bus and memory utilisation will provide improved deferred transaction support, with cache line size optimised to conserve bandwidth. The dedicated full-speed Level 2 bus will free the system bus for multiprocessing, with increased page size of up to 256MB.

The cartridge for Merced includes heat dissipation technology on top of the die, a "cost-effective" performance substrate, Intel-designed static cache RAM, a full-speed cache bus and separate signal and power connections for signal integrity.